GENESIS Technical Overview

CONFIDENTIAL

PROPERTY OF SEGA

68000 @8 MHz

main CPU
1 MByte (8 Mbit) ROM Area
64 KByte RAM Area

VDP (Video Display Processor)

dedicated video display processor
- controls playfield & sprites
- capable of DMA
- Horizontal & Vertical interrupts
64 KBytes of dedicated VRAM (Video Ram)
64 x 9-bits of CRAM (Color RAM)

Z80 @4 MHz

controls PSG (Programmable Sound Generator) & FM Chips
8 KBytes of dedicated Sound Ram

VIDEO:

NOTE: Playfield and Sprites are character-based
Display Area (visual)
- 40 chars wide x 28 chars high
  - each char is 8 x 8 pixels
  - pixel resolution = 320 x 224
- 3 Planes
  - 2 scrolling playfields
  - 1 sprite plane
  - definable priorities between planes
- Playfields:
  - 6 different sizes
  - 1 playfield can have a "fixed" window
  - playfield map
    - each char position takes 2 Bytes, that includes:
      - char name (10 bits); points to char definition
      - horizontal flip
      - vertical flip
      - color palette (2 bits); index into CRAM
      - priority
  - scrolling:
    - 1 pixel scrolling resolution
    - horizontal:
      - whole playfield as unit
      - each character line
      - each scan line
    - vertical:
      - whole playfield as unit
      - 2 char wide columns
- Sprites:
  - 1 x 1 char up to 4 x 4 chars
  - up to 80 sprites can be defined
  - up to 20 sprites displayed on a scan line
  - sprite priorities
- Character Definitions
  - 4 bits/pixel; points to color register
  - 4 bytes/scanline of char
  - 32 bytes for complete char definition
  - playfield & sprite chars are the same!

COLOR:

Uses CRAM (part of the VDP)
- 64 9-bit wide color registers
  - 3 bits of Red
  - 3 bits of Green
  - 3 bits of Blue
  - 4 palettes of 16 colors
    - 0th color (of each palette) is always transparent

OTHER:

DMA
- removes the 68000 from the BUS
- can move 205 Bytes/scanline during VBLANK
  - there are 36 scanlines during VBLANK
  - DMA can move 7380 Bytes during VBLANK
Horizontal & Vertical interrupts

SOUND:

Z80 controls:
- PSG (TI 76489 chip)
- FM chip (Yamaha YM 2612)
  - 6-channel stereo
- Z80 can access ROM data
- 8 KBytes RAM

HARDWARE:

2 controllers
- joypad
- 3 buttons
- Start button
1 external port
2 video-outs (RF & RGB)
audio jack
volume control (for audio jack)

* INDEX *

1. MEMORY MAP

§ 1 MEGA DRIVE 16BIT MODE

68000 MEMORY MAP
Z80 MEMORY MAP
68000 ACCESS TO Z80 MEMORY
I/O AREA
CONTROL AREA
VDP AREA
2. VDP 315-5313 (Video Display Processor)

TERMINOLOGY
§ 1 DISPLAY SPECIFICATION
§ 2 VDP STRUCTURE

CTRL
VRAM
CRAM
VSRAM
DMA

§ 3 INTERRUPTS

VERTICAL INTERRUPT
HORIZONTAL INTERRUPT
EXTERNAL INTERRUPT

§ 4 VDP INTERFACE

$C00000 (DATA CHANNEL)
$C00004 (CONTROL CHANNEL)
$C00008 (HV COUNTER)

§ 5 VDP REGISTER

Reg. # 0 - Reg. # 3
Reg. # 4 - Reg. #10
Reg. #11 - Reg. #14
Reg. #15 - Reg. #18
Reg. #19 - Reg. #23

§ 6 ACCESS VDP RAM

ADDRESS SETTING
VRAM ACCESS
CRAM ACCESS
VSRAM ACCESS
ACCESS TIMING
HV COUNTER

§ 7 DMA

MEMORY TO VRAM
VRAM FILL
VRAM COPY
DMA ABILITY

§ 8 SCROLL

SCREEN SIZE
HORIZONTAL SCROLL
VERTICAL SCROLL
SCROLL PATTERN
PATTERN NAME

§ 9 WINDOW

POSITION
PRIORITY
PATTERN NAME

§ 10 SPRIT_E

POSITION
ATTRIBUTE
SIZE
ABILITY
PRIORITY (SPRITES)
PATTERN GENERATOR

§ 11 PRIORITY
§ 12 COLOR PALETTE
§ 13 INTERLACE MODE
3. 8/16 BIT COMPATIBILITY

MARK III (MS - JAPAN)
MS
RAM CARD
4. I/O

§ 1 VERSION NO.
§ 2 I/O
§ 3 MEMORY MODE
§ 4 Z80 CONTROLS

Z80 BUSREQ
Z80 RESET

§ 5 Z80 AREA

SOUND RAM
SOUND CHIP
BANK REGISTER
5. VRAM MAPPING
6. APPEND

1. MEMORY MAP

§ 1 MEGA DRIVE 16 BIT MODE (AS DISTINCT FROM MASTER SYSTEM COMPATIBILITY MODE)

_ 68K MEMORY MAP _

_ Z80 MEMORY MAP _

_ 68000 ACCESS TO Z80 MEMORY _

_ I/O AREA _

_ CONTROL AREA _

_ VDP AREA _

2. VDP 315 - 5313

(Video Display Processor)

The VDP controls screen display. VDP has graphic modes IV and V. Where Mode IV is for compatibility with the MASTER SYSTEM and V is for the new Mega drive functions. There are no advantages to using mode IV. so it is assumed that all Mega drive development will use mode V. In Mode V. the VDP display has 4 planes: SPRITE, SCROLL A/WINDOW, SCROLL B, and BACKGROUND.

GRAPHIC IV MODE (COMPATIBILITY MODE)

GRAPHIC V MODE (16 BIT MODE)

_ TERMINOLOGY _

1. A unit of Position on X Y coordinates is called a "DOT".

2. A minimum unit of display is called a "PIXEL".

3. "CELL" means an 8 (pixel) x 8 (pixel) pattern.

4. SCROLL indicated a repositionable screen-spanning play field.

5. CPU usually indicates the 68000.

6. VDP stands for Video Display Processor.

7. CTRL stands for Control.

8. VRAM stands for VDP RAM, the 64K bytes area of RAM accessible only through the VDP.

9. CRAM stands for Color RAM, 64 9 bit words inside the VDP chip.

10. VSRAM stands for vertical Scroll RAM. 40 10-bit words inside the VDP chip.

11. DMA stands for Direct Memory Access, the process by which the VDP performs high speed fills or memory copies.

12. PSG stands for Programmable sound Generator. A class of low-capability Sound chips. The Mega drive contains a Texas Instruments 76489 PSG chip.

13. FM stands for Frequency Modulation, a class of high-capability sound chip. The Mega drive contains a Yamaha 2612 FM chip.

§ 1 DISPLAY SPECIFICATION

DISPLAY SPECIFICATION OUTLINE

DISPLAY SIZE THERE ARE TWO MODES:
32*28 CELL (256*224 PIXEL)
40*28 CELL (320*224 PIXEL)
CHARACTER GENERATOR 8*8 CELLS 1300-1800 depending on general system configuration.
SCROLL PLAYFIELDS Two scrolling play fields. whose size in cells is selectable from:
32*32, 32*64, 32*128,
64*32, 64*64, 128*32
SPRITE Sprite size is programmable on a sprite by sprite basis. with the following choices:
8*8, 8*16, 8*24, 8*32
16*8, 16*16, 16*24, 16*32
24*8, 24*16, 24*24, 24*32
32*8, 32*16, 32*24, 32*32
There are 64 sprites available when the screen is in 32 cell wide mode. Or 80 when the screen is in 40 cell wide mode.
WINDOW 1 window associated with the Scroll A play field.
COLORS 64 colors/512 possibilities

For PAL (the European Television 50HZ standard), a vertical size of 30 cells (240 dots) is selectable. The VDP supports both NTSC and PAL television standards. In both cases, the screen is divided into active scan, where the picture is displayed, and vertical retrace (or vertical blanking) where the monitor prepares for the next display.

Numbers of rasters in a screen are as follows:

Lines/Screen VCELL LINE NO.
(DISPLAY) LINE NO.
(RETRACE)
NTSC
262
28
224 RASTER
38 RASTER
PAL
312
28
224 RASTER
98 RASTER
PAL
312
30
240 RASTER
82 RASTER

§2 VDP STRUCTURE

The CPU controls the VDP by special I/O memory locations.

_ CTRL (Control) _

This controls REGISTER, VRAM, CRAM, VSRAM, DMA DISPLAY, etc.

_ VRAM (VDP RAM) _

General purpose storage area for display data.

_ CRAM (COLOR RAM) _

64 colors divided into 4 palettes of 16 colors each.

_ VSRAM (Vertical scroll RAM) _

Up to 20 different vertical scroll values each for scrolling play fields A and B.

_ DMA (Direct Memory Access) _

The VDP may move data at high speed from CPU memory to VRAM, CRAM, and VSRAM instead of the CPU, by taking the 68000 off the bus and doing DMA itself. The VDP can also fill the VRAM with a constant, or copy from VRAM to VRAM without disturbing the 68000.

§ 3 INTERRUPT

There are three interrupts: Vertical, Horizontal, and External. You can control each interrupt by the IE0, IE1, and IE2 bits in the VDP registers. The interrupts use the AUTO-VECTOR mode of the 68000 and are at levels 6, 4, and 2 respectively. The level 6 vertical interrupt having the highest priority.

IE0 VInterrupt (LEVEL6)
IE1 HInterrupt (LEVEL4)
IE2 External Interrupt (LEVEL2)
1 : Enable
0 : Disable

_ VERTICAL INTERRUPT (V-INT) _

The vertical interrupt occurs just after V retrace.

_ HORIZONTAL INTERRUPT (H-INT) _

The horizontal interrupt occurs just before H retrace.

The VDP loads the required display information, including all required register values, for the line in about 36 clocks, thus the CPU can control the display of the next line but not the line on which the interrupt occurs.

The horizontal interrupt is controlled by a line counter in register #10. If this line counter is changed at each interrupt, the desired spacing of interrupts may be achieved.

Thus: If Register #10 equals 00h then the interrupt occurs every line.
If Register #10 equals 01h then the interrupt occurs every other line.
If Register #10 equals 02h then the interrupt occurs every third line.

_ EXTERNAL INTERRUPT (EX-INT) _

The external interrupt is generated by a peripheral device (gun, modem) and stops the counter for later examination by the CPU.

Please see other sections of this manual for information about the H, V counter and the initialization of the external interrupt.

§ 4 VDP PORT

The VDP ports are at location $C00000 in the 68000 memory space.

UPPER BYTE | LOWER BYTE
$ C00000 DATA PORT
$ C00002 "
$ C00004 CONTROL PORT
$ C00006 "
$ C00008 HV COUNTER
$ C0000A PROHIBITED
$ C0000C PROHIBITED
$ C0000E PROHIBITED
$ C00010 PROHIBITED PSG

_ $ C00000 (DATA PORT) _

READ/WRITE: VRAM, VSRAM, CRAM

$C00000 DT15 DT14 DT13 DT12 DT11 DT10 DT9 DT8 ( D15 ~ D8 )
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 ( D7 ~ D0 )
* $C00000 and $C00002 are functionally equivalent.

_ $ C00004 (CONTROL PORT) _

READ : STATUS REGISTER

$C00004 * * * * * * EMPT FULL ( D15 ~ D8 )
F SOVR C ODD VB HB DMA PAL ( D7 ~ D0 )

* NO USE

EMPT 1: WRITE FIFO EMPTY
0:
FUL 1: WRITE FIFO FULL
0:
F 1: V interrupt happened.
SOVR 1: Sprites overflow occurred, too many in one line.
Over 17 in 32 cell mode.
Over 21 in 40 cell mode.
C 1: Collision happened between non-zero pixels in two sprites.
0:
ODD 1: Odd frame in interlace mode.
0: Even frame in interlace mode.
VB 1: During V blanking
0:
HB 1: During H blanking
0:
DMA 1: DMA BUSY
0:
PAL 1: PAL MODE
0: NTSC MODE

WRITE1 : REGISTER SET

$C00004 1 0 0 RS4 RS3 RS2 RS1 RS0 ( D15 ~ D8 )
D7 D6 D5 D4 D3 D2 D1 D0 ( D7 ~ D0 )
* $C00004 and $C00006 are functionally equivalent.

RS4 ~ RS0 : Register No.
D7 ~ D0 : Date

* You must use word or long word access to VDP ports when setting the registers. Long word access is equivalent to two word accesses, with D31-D16 written first.

WRITE2 : ADDRESS SET

1st CD1 CD0 A13 A12 A11 A10 A9 A8 ( D15 ~ D8 )
$ C00004 A7 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 CD5 CD4 CD3 CD2 0 0 A15 A14 ( D7 ~ D0 )

CD5 ~ CD0 : ID CODE
A15 ~ A0 : DESTINATION RAM ADDRESS

ACCESS MODE CD5 CD4 CD3 CD2 CD1 CD0
VRAM WRITE 0 0 0 0 0 1
CRAM WRITE 0 0 0 0 1 1
VSRAM WRITE 0 0 0 1 0 1
VRAM READ 0 0 0 0 0 0
CRAM READ 0 0 1 0 0 0
VSRAM READ 0 0 0 1 0 0

* You must use word or long word when performing these operations.

_ $ C00008 (HV Counter) _

NON INTERLACE MODE

$ C00008 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 ( D15 ~ D8 )
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 ( D7 ~ D0 )

INTERLACE MODE

$ C00008 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC8 ( D15 ~ D8 )
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 ( D7 ~ D0 )

HC8 ~ HC1 : H COUNTER
VC8 ~ VC0 : V COUNTER

§ 4 VDP REGISTER

VDP has write only register #0 through #23 and read only status register total 25 register. These are two modes for register settings. One is mode 4 and another is mode 5. We tell you about mode 5 in this section and about mode 4 see MARK section. If you change mode in one frame you can get various effects.

MODE SET REGISTER No. 1

MSB LSB
REG. # 0 0 0 0 IE1 0 1 M3 0

IE1 1: Enable H interrupt (68000 Level 4)
0: Disable H interrupt (REG #10)
M3 1: HV. Counter stop
0: Enable read HV. counter

MODE SET REGISTER No. 2

MSB LSB
REG. # 1 0 DISP IE0 M1 M2 1 0 0

DISP 1: Enable Display
0: Disable Display
IE0 1: Enable V interrupt (68000 Level 6)
0: Disable V interrupt
M1 1: DMA Enable
0: DMA Disable
M2 1: V 30 cell mode (PAL mode)
0: V 28 cell mode (PAL mode, always 0 in NTSC mode)

PATTERN NAME TABLE BASE ADDRESS FOR SCROLL A

MSB LSB
REG. # 2 0 0 SA15 SA14 SA13 0 0 0

VRAM ADDR $XXX0_0000_0000_0000

PATTERN NAME TABLE BASE ADDRESS FOR WINDOW

MSB LSB
REG. # 3 0 0 WD15 WD14 WD13 WD12 WD11 0

WD11 should be 0 in H40 cell mode

VRAM ADDR $ XXXX_X000_0000_0000 (H 32 cell mode)

VRAM ADDR $ XXXX_0000_0000_0000 (H 40 cell mode)

PATTERN NAME TABLE BASE ADDRESS FOR SCROLL B

MSB LSB
REG. # 4 0 0 0 0 0 SB15 SB14 SB13

VRAM ADDR $XXX0_0000_0000_0000

SPRITE ATTRIBUTE TABLE BASE ADDRESS

MSB LSB
REG. # 5 0 AT15 AT14 AT13 AT12 AT11 AT10 AT9

AT9 should be 0 in H 40 cell mode

VRAM ADDR $XXXX_XXX0_0000_0000 ( 32 cell )

VRAM ADDR $XXXX_XX00_0000_0000 ( 40 cell )

MSB LSB
REG. # 6 0 0 0 0 0 0 0 0

BACKGROUND COLOR

MSB LSB
REG. # 7 0 0 CPT1 CPT0 COL3 COL2 COL1 COL0

CPT1,0 : COLOR PALLET

COL3 ~ 0 : COLOR CODE

MSB LSB
REG. # 8 0 0 0 0 0 0 0 0

MSB LSB
REG. # 9 0 0 0 0 0 0 0 0

H INTERRUPT REGISTER

MSB LSB
REG. # 10 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

This register makes H interrupt timing by number of Raster

H interrupt is enabled by IE=1

MODE SET REGISTER No. 3

MSB LSB
REG. # 11 0 0 0 0 IE2 VSCR HSCR LSCR

IE2 1: Enable external interrupt (68000 Level 2)

0: Disable external interrupt

* See INTERRUPT and SYSTEM I/O

VSCR: V scroll mode HSCR, LSCR: H scroll mode

VSCR FUNCTION HSCR LSCR FUNCTION
0 FULL SCROLL 0 0 FULL SCROLL
1 EACH 2 CELL SCROLL 0 1 PROHIBITED
1 0 EACH 1 CELL SCROLL
1 1 EACH 1 LINE SCROLL

* BOTH SCROLL A AND B

MODE SET REGISTER No. 4

MSB LSB
REG. # 12 RS0 0 0 0 S/TE LSM1 LSM0 RS1

RS0 0: Horizontal 32 cell mode
1: Horizontal 40 cell mode
RS1 0: Horizontal 32 cell mode
1: Horizontal 40 cell mode
* You should set same No. in RS0, RS1.
32 cell 0000_XXX0
40 cell 1000_XXX1
S/TE 1: Enable SHADOW and HIGHLIGHT.
0: Disable SHADOW and HIGHLIGHT.
LSM1, LSM0 : Interlace mode setting

LSM1 LSM0 FUNCTION
0 0 NO INTERLACE
0 1 INTERLACE
1 0 PROHIBITED
1 1 INTERLACE (Double Resolution)

H SCROLL DATA TABLE BASE ADDRESS

MSB LSB
REG. # 13 0 0 HS15 HS14 HS13 HS12 HS11 HS10

VRAM ADDR $XXXX_XX00_0000_0000

MSB LSB
REG. # 14 0 0 0 0 0 0 0 0

AUTO INCREMENT DATA

This register controls bias number of increment data.

MSB LSB
REG. # 15 INC7 INC6 INC5 INC4 INC3 INC2 INC1 INC0

INC7 ~ 0: Bias number ( 0 ~ $FF )

This number is added automatically after ram access.

SCROLL SIZE

MSB LSB
REG. # 16 0 0 VSZ1 VSZ0 0 0 HSZ1 HSZ0

VSZ1 VSZ0 FUNCTION HSZ1 HSZ0 FUNCTION
0 0 V 32 cell 0 0 H 32 cell
0 1 V 64 cell 0 1 H 64 cell
1 0 PROHIBITED 1 0 PROHIBITED
1 1 V 128 cell 1 1 H 128 cell

* Both of scroll A and B

WINDOW H POSITION

MSB LSB
REG. # 17 RIGT 0 0 WHP5 WHP4 WHP3 WHP2 WHP1

RIGT 0: Window is in left side from base point.
1: Window is in right side from base point.
WHP5 ~ 1 Base pointer 0=Left Side
1=1 cell right
2...

WINDOW V POSITION

MSB LSB
REG. # 18 DOWN 0 0 WVP4 WVP3 WVP2 WVP1 WVP0

DOWN 0: Window is in upper side from base point.
1: Window is in lower side from base point.
WVP4 ~ 0 Base pointer 0=Upper side
1= 1 cell down
2...

DMA LENGTH COUNTER LOW

MSB LSB
REG. # 19 LG7 LG6 LG5 LG4 LG3 LG2 LG1 LG0

DMA LENGTH COUNTER HIGH

MSB LSB
REG. # 20 LG15 LG14 LG13 LG12 LG11 LG10 LG9 LG8

LG15 ~ 0: DMA LENGTH COUNTER

DMA SOURCE ADDRESS LOW

MSB LSB
REG. # 21 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1

DMA SOURCE ADDRESS MID

MSB LSB
REG. # 22 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9

DMA SOURCE ADDRESS HIGH

MSB LSB
REG. # 23 DMD1 DMD0 SA22 SA21 SA20 SA19 SA18 SA17

SA22 ~ 1 : DMA Source address

DMD1, 0 : DMA MODE

DMD1 DMD0 FUNCTION
0 SA23 MEMORY TO VRAM
1 0 VRAM FILL
1 1 VRAM COPY

§ 6 ACCESS VDP RAM

_ RAM ADDRESS SETTING _

You can access VRAM CRAM and VSRAM after writing 32 bits of control data to $C00004 or $C00006. You have to use word or long word when addressing. If you use long word D31 - D16 is 1st, D15 - D0 2nd.

1st CD1 CD0 A13 A12 A11 A10 A9 A8 ( D15 ~ D8 )
$ C00004 A7 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 CD5 CD4 CD3 CD2 0 0 A15 A14 ( D7 ~ D0 )

CD5 ~ CD0 : ID CODE

A15 ~ A0 : DESTINATION RAM ADDRESS

CD5 CD4 CD3 CD2 CD1 CD0
VRAM WRITE 0 0 0 0 0 1
CRAM WRITE 0 0 0 0 1 1
VSRAM WRITE 0 0 0 1 0 1
VRAM READ 0 0 0 0 0 0
CRAM READ 0 0 1 0 0 0
VSRAM READ 0 0 0 1 0 0

_ VRAM ACCESS _

VRAM address range from 0 to 0FFFFH, 64K bytes total. VRAM access addressing is as follow when writing:

1st 0 1 A13 A12 A11 A10 A9 A8 ( D15 ~ D8 )
$ C00004 A7 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 C 0 0 0 0 0 A15 A14 ( D7 ~ D0 )

A15 ~ A0 : VRAM address

Data D15 D14 D13 D12 D11 D10 D9 D8 ( D15 ~ D8 )
$ C00000 D7 D6 D5 D4 D3 D2 D1 D0 ( D7 ~ D0 )

D15 ~ D0 : VRAM data

When you use long word D31 ~ D16 is 1st. D15 ~ D0 2nd. When you do byte writing, data is D7 ~ D0, and may be written to $C00000 or $C00001.

VRAM address is increased by the value of REGISTER # 15. independent data size. VRAM address A0 is used in the calculation of the address increment, but is ignored during address decoding.

VRAM addressing and decoding are as follows:

the CRAM address decode uses A15 ~ A1, and A0 specifies the data write format. Write data can not cross a word boundary high and low bytes are exchanged if A0=1.

(EXAMPLE)

START ADDRESS: 0 REG. #15=2

START ADDRESS: 0 REG. #15=1

START ADDRESS: 1 REG. #15=2

START ADDRESS: 1 REG. #15=1

VRAM READ

1st 0 0 A13 A12 A11 A10 A9 A8 ( D15 ~ D8 )
$ C00004 A7 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 0 0 0 0 0 A15 A14 ( D7 ~ D0 )

A15 ~ A0 : VRAM address

Data D15 D14 D13 D12 D11 D10 D9 D8 ( D15 ~ D8 )
$ C00000 D7 D6 D5 D4 D3 D2 D1 D0 ( D7 ~ D0 )

D15 ~ D0 : VRAM data

The data is always read in word units. A0 is ignored during the read; no swap of bytes occurs if A0=1. Subsequent reads are from address incremented by REGISTER #15. A0 is used in calculation of the next address.

_ CRAM ACCESS _

The CRAM contains 128 bytes, addresses 0 to 7FH. For word wide writes to the CRAM, use:

1st 1 1 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 0 0 0 0 0 0 0 ( D7 ~ D0 )

A6 ~ A0 : VRAM address

Data 0 0 0 0 B2 B1 B0 0 ( D15 ~ D8 )
$ C00000 G2 G1 G0 0 R2 R1 R0 0 ( D7 ~ D0 )

D15 ~ D0 are valid when we use word for data set. If the writes are byte wide, write the high byte to $C00000 and the low byte to $C00001. A long word wide access is equivalent to two sequential word wide accesses. Place the first data in D31 - D16 and the second data in D15 - D0. The data may be written sequentially; the address is incremented by the value of REGISTER #15 after every write, independent of whether the width is byte of word.

Note that A0 is used in the increment but not in address decoding, resulting in some interesting side-effects if writes are attempted at odd addresses.

For word wide reads from the CRAM, use:

1st 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 0 1 0 0 0 0 0 ( D7 ~ D0 )

A6 ~ A0 : VRAM address

Data * * * * B2 B1 B0 * ( D15 ~ D8 )
$ C00000 G2 G1 G0 * R2 R1 R0 * ( D7 ~ D0 )

_ VSRAM ACCESS _

The VSRAM contains 80 bytes, addresses 0 to 4FH. For word wide writes to the VSRAM, use:

1st 0 1 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 0 0 1 0 0 0 0 ( D7 ~ D0 )

A6 ~ A0 : VSRAM address

Data VS10 VS9 VS8 ( D15 ~ D8 )
$ C00000 VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0 ( D7 ~ D0 )

VS10 - VS0 : V quantity of scroll

If you use word for data and valid in D15 ~ D0. D15 - D0 are valid when we use word for data set. If the writes are byte wide, write the high byte to $C00000 and the low byte to $C00001. A long word wide access is equivalent to two sequential word wide accesses. Place the first data in D31 - D16 and the second data in D15 - D0. The data may be written sequentially; the address is incremented by the value of REGISTER #15 after every write, independent of whether the width is byte of word.

Note that A0 is used in the increment but not in address decoding, resulting in some interesting side-effects if writes are attempted at odd addresses.

For word wide reads from the VSRAM, use:

1st 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 A6 A5 A4 A3 A2 A1 A0 ( D7 ~ D0 )

2nd 0 0 0 0 0 0 0 0 ( D15 ~ D8 )
$ C00004 0 0 0 1 0 0 0 0 ( D7 ~ D0 )

A6 ~ A0 : VSRAM address

Data VS10 VS9 VS8 ( D15 ~ D8 )
$ C00000 VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0 ( D7 ~ D0 )

VS10 ~ VS0 : V quantity of scroll

_ ACCESS TIMING _

The CPU and CDP access CRAM, CRAM, and VSRAM using timesharing. Because the VDP is very busy during the active scan, the CPU accesses are limited. However, during vertical blanking the CPU may access the CDP continuously.

The number of permitted accesses by the CPU additionally depends on whether the screen is in 32 cell mode or 40 cell mode. Additionally the access size depends on the RAM type; a VRAM access is byte wide, but CRAM and CSRAM are wor wide.

For example, in 32 cell mode, the CPU may access the VRAM 16 times during horizontal scan in a single line. Each access is a byte write, so this amounts to 2 words. However CRAM and CSRAM though sharing the 16 time limit, are word accesses so that 16 words may be written in a single line.

Although there is a four-word FIFO, if writes are done in a tight loop during active scan the FIFO will fill up and the CPU will eventually end up waiting to write.

The maximum wait times are:

DISPLAY MODE MAXIMUM WAITING TIME
H 32 cell Approximate 5.96 µsec
H 40 cell Approximate 4.77 µsec

As the CPU has unlimited access to the RAMs during vertical blanking, the wait case never arises.

_ HV COUNTER _

The HV counter's function is to give the horizontal and vertical location of the television beam. If the "M3" bit of REGISTER #0 is set, the HV counter will then freeze when trigger signal HL goes high, as well as triggering a level 2 interrupt.

M3 COUNTER LATCH MODE
0 COUNTER IS NOT LATCHED BY TRIGGER SIGNAL
1 COUNTER IS LATCHED BY TRIGGER SIGNAL

M3: REGISTER # 0

NON INTERLACE MODE

$ C00008 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 ( D15 ~ D8 )
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 ( D7 ~ D0 )

INTERLACE MODE

$ C00008 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC8 ( D15 ~ D8 )
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 ( D7 ~ D0 )

V-COUNTER : VC7 ~ VC0 H-COUNTER : HC8 ~ HC1

DISPLAY MODE COUNTER DATA DISPLAY MODE COUNTER DATA
V 28 CELL 0 ~ DFH H 32 CELL 0 ~ 7FH
V 30 CELL 0 ~ EFH H 40 CELL 0 ~ 9FH

The counter only has eight bits each for H and V, so interlace mode and 40 cell (320 dots) modes present some problems. During interlace mode, the LSB of the vertical position is replaced by the new MSB. And the horizontal resolution problem is solved by ALWAYS dropping the LSB.

CAUTION:

As the HV counter's value is not valid during vertical blanking, check to be sure that it is active scan before using the value.

§ 7 DMA TRANSFER

DMA (Direct Memory Access) is a high speed technique for memory accesses to the VRAM. CRAM and VSRAM. During DMA VRAM, CRAM and VSRAM occur at the fastest possible rate (please see the section on access timing). There are three modes of DMA access. as can be seen below. all of which may be done to VRAM or CRAM or VSRAM. The 68K is stopped during memory to VRAM/CRAM/VSRAM DMA, but the Z80 continues to run as long as it does not attempt access to the 68K memory space.

The DMA is quite fast during VBLANK. about double the tightest possible 68K Top's speed, but during active scan the speed is the same as a 68K loop.

Please note that after this point. VRAM is used as a generic term for VRAM/CRAM/VSRAM.

DMD1 DMD0 DMA MODE SIZE
0 SA23 A. MEMORY TO V-RAM WORD to BYTE(H)&(L)
1 0 B. VRAM FILL BYTE to BYTE
1 1 C. VRAM COPY BYTE to BYTE

DMD1, DMD0: REG #23 * DMD0=SA23

Source address are $000000-$3FFFFF (ROM) and $FF0000--$FFFFFF (RAM)

for memory to VRAM transfers. In the case of ROM to VRAM transfers, a hardware feature causes occasional failure of DMA unless the following two conditions are observed:

--The destination address write (to address $C00004) must be a word write.

--The final write must use the work RAM.

There are two ways to accomplish this, by copying the DMA program into RAM or by doing a final "move.w ram address $C00004"

_ MEMORY TO VRAM _

The function transfers data from 68K memory to VRAM, CRAM or VSRAM. During this DMA all 68K processing stops. The source address is $000000-$3FFFFF for ROM or $FF0000-$FFFFFF for RAM. The DMA reads are word wide. writes are byte wide for VRAM and word wide for CRAM and VSRAM. The destination is specified by:

CD2 CD1 CD0 MEMORY TYPE
0 0 1 VRAM
0 1 1 CRAM
1 0 1 VSRAM

Setting of DMA

(A) M1 (REG. #1)=1 : DMA ENABLE

(B) Increment No. set to #15 (normally 2)

(D) Source address and DMA mode set into #21, #22, #23.

(E) Set the destination address.

(F)*VDP gets the CPU bus.

(G)*DMA start.

(H)*VDP releases the CPU bus.

(I) M1 have to be 0 after confirmation of DMA finish : DMA DISABLED

DMA starts after (E).

You must set M1=1 only during DMA otherwise we cannot guarantee the operation. Source address were increased with +2 and destination address increased with content of register #15.

Content : of register. Register #1 has another bits.