// implementation of EA flash chip 16V8R; pin 1 CLK; pin 20 VCC; pin 2 A18; pin 19 CLKO; // feedback to CLK input pin 3 A19; pin 18 D7; // D7 I/O pin 4 A20; pin 17 D6; // D6 input pin 5 A21; pin 16 !ROM_CE; // ROM chip enable output pin 6 !CE_L; pin 15 SCL; // I2C serial clock pin 7 !WR_L; pin 14 SDA; // I2C serial data pin 8 !OE; pin 13 !TIME; // chip select for A130xx? pin 9 !RES; pin 12 SDA_OE; // used for feedback term from SDA latch pin 10 GND; pin 11 GAL_OE; // 16V8 !OE input should be grounded // notes: // W1=ROM-30 left=A18 right=VCC left=32-pin, right=28-pin // W2=U1-31 left=A19 right=WR_H left=eprom, right=flash // W3=U2-31 left=A19 right=WR_L left=eprom, right=flash // W4=ROM-1 left=A19 right=VCC left=flash, right=eprom // W5=ROM_CE bypass when GAL not installed // R1=SDA pull-up // U1=even/high ROM // U2=odd/low ROM // U3=GAL16V8 // U4=24Cxx DIP8 // U4A=24Cxx SOIC8 // U4B=24Cxx TSSOP8, with trace cut provision for second EEPROM // SDA/SCL clock for writing latches at 200000-2FFFFF, when CE_L and WR_L are asserted // also clocked on reset //CLKO = CE_L & !OE & WR_L & A21 & !A20 | RES; CLKO = CE_L & !OE & WR_L & A21 & !A20; // CLKO is output-only CLKO.OE = 1; // D7 = SDA input when D7.OE is asserted D7 = SDA; // read SDA at 200000-2FFFFF, when CE_L and OE are asserted D7.OE = CE_L & OE & A21 & !A20; // D6 is input-only D6.OE = 0; // ROM at 000000 - 1FFFFF, can add other address lines later, when CE_L asserted ROM_CE = CE_L & !A21; // !ROM_CE is output-only ROM_CE.OE = 1; // on clock, SCL = D6 and cleared during reset //SCL := D6 & RES; SCL := D6; // SCL is registered and uses pin 11 for OE //SCL.OE = n/a; (no OE term for registered outputs) // SDA is driven high by pull-up resistor, driven low by SDA_OE SDA = 0; // feedback for SDA output enable SDA.OE = SDA_OE; // !TIME is input-only TIME.OE = 0; // on clock, SDA = D7 and set during reset //!SDA_OE := !D7 & RES; SDA_OE := D7; // SDA_OE is registered and uses pin 11 for OE //SDA_OE.OE = n/a; (no OE term for registered outputs) test CLKO ROM_CE; test [ CLK=C D7 !D6 -> SDA_OE SDA=Z !SCL ]; // load 01 test [ !CLK !D7 D6 -> SDA_OE SDA=Z !SCL ]; // latched test [ CLK=C !D7 D6 -> !SDA_OE !SDA SCL ]; // load 10 test [ !CLK D7 !D6 -> !SDA_OE !SDA SCL ]; // latched