Chip type = 16V8R
Source file: genesis4.pal
*
QP20*    N 20 pins * 
QF2194*  N 2194 fuses *
QV0036*  N 36 test vectors *
F0*      N default fuse state *
G0*      N don't blow the security fuse *

L0000
11111111111111111111111111111111
11111111101101111011101101111111
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L0256
11111111101101111011111110111111
11111111111111111111110111111111
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L0512
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L0768
11111111111111111111111111111111
11111111111110111011111111111111
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L1024
11111111110111111111111111111111
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L1280
11111111111111111111111111111110
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L1536
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L1792
11111101111111111111111111111111
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*

L2048
11101111*

L2056
0000000000000000000000000000000000000000000000000000000000000000*

L2120
11110110*

L2128
1111111111111111111111111111111111111111111111111111111111111111*

L2192
0*

L2193
1*

C2BCB*

N test vectors *

V0001 NNN00000NNNNNNNLNNLN*
V0002 NNN00001NNNNNNNLNNLN*
V0003 NNN00010NNNNNNNLNNLN*
V0004 NNN00011NNNNNNNLNNLN*
V0005 NNN00100NNNNNNNHNNLN*
V0006 NNN00101NNNNNNNHNNLN*
V0007 NNN00110NNNNNNNHNNLN*
V0008 NNN00111NNNNNNNHNNLN*
V0009 NNN01000NNNNNNNHNNLN*
V0010 NNN01001NNNNNNNHNNHN*
V0011 NNN01010NNNNNNNHNNLN*
V0012 NNN01011NNNNNNNHNNLN*
V0013 NNN01100NNNNNNNHNNLN*
V0014 NNN01101NNNNNNNHNNLN*
V0015 NNN01110NNNNNNNHNNLN*
V0016 NNN01111NNNNNNNHNNLN*
V0017 NNN10000NNNNNNNLNNLN*
V0018 NNN10001NNNNNNNLNNLN*
V0019 NNN10010NNNNNNNLNNLN*
V0020 NNN10011NNNNNNNLNNLN*
V0021 NNN10100NNNNNNNHNNLN*
V0022 NNN10101NNNNNNNHNNLN*
V0023 NNN10110NNNNNNNHNNLN*
V0024 NNN10111NNNNNNNHNNLN*
V0025 NNN11000NNNNNNNHNNLN*
V0026 NNN11001NNNNNNNHNNLN*
V0027 NNN11010NNNNNNNHNNLN*
V0028 NNN11011NNNNNNNHNNLN*
V0029 NNN11100NNNNNNNHNNLN*
V0030 NNN11101NNNNNNNHNNLN*
V0031 NNN11110NNNNNNNHNNLN*
V0032 NNN11111NNNNNNNHNNLN*
V0033 CNNNNNNNNNNHNZLN01NN*
V0034 0NNNNNNNNNNHNZLN10NN*
V0035 CNNNNNNNNNNLNLHN10NN*
V0036 0NNNNNNNNNNLNLHN01NN*

0000