SECTION 9

SUPPLEMENTARY INFORMATION

9-1 AUXILIARY CONNECTOR

Figure 9-1.1. J3-Auxiliary Connector Pinout (D-Subminiature, Female)

13 12 11 10 9 8 7 6 5 4 3 2 1
25 24 23 22 21 20 19 18 17 16 15 14

Pin		Pin
1	PROTECTIVE GROUND	14
2	SERIAL DATA (OUT) (RS-232C)	15
3	SERIAL DATA (IN) (RS-232C)	16
4	REQUEST-TO-SEND (OUT) (RS-232C)	17
5	CLEAR-TO-SEND (IN) (RS-232C)	18
6	DATA-SET-Ready (NOT IMPLEMENTED)	19
7	SIGNAL GROUND (RS-232C)	20	DATA TERMINAL READY (OUT) (RS-232C)
8		21
9	EXT BREAK-IN (ASYNCHRONOUS)	22	¬RUN (OUT)
10	EXT BREAK-IN (SYNCHRONOUS)	23	+ 5 VOLTS (OUT)
11	TRACE HOLD (IN)	24	GROUND
12	BKPT A and SA START (OUT)	25	SIGNATURE CLOCK (OUT)
13	BKPT B and SA STOP (OUT)

Pins without associated signals shown are not connected within the EM-180.

The functions of the auxiliary connector signals are summarized below:

Pin 1	Protective Ground: Connected in the EM-180 to the chassis, and from the chassis to the protective ground terminal of the primary power input connector.
Pin 2	Serial Data Out: This signal is driven to nominal ± 12 volt levels by an RS-232C compatible driver. See Section 9-3 (Serial Interface) for format of serial data.
Pin 3	Serial Data In: The EM-180 accepts data on this pin that has voltage levels as specified by the EIA RS-232C specification and the format given in Section 9-3.
Pin 4	Request to Send: This signal is driven to nominal ± 12 volt levels by an RS-232C compatible driver. The state of this signal is determined by software in the EM-180.
Pin 5	Clear to Send: The EM-180 accepts a signal on this pin having RS-232C voltage levels. The state of this signal may be read by the EM-180 control software.

Pin 7	Signal Ground: Connected in the EM-180 to the system logic ground which is isolated from the protective ground (Pin 1). Note, however that this ground is connected to the emulator probe ground pin; then when the EM-180 is connected to the target equipment, the target system logic ground and the EM-180 logic ground are connected together and to the ground system of the equipment plugged into the Auxiliary Connector.
Pin 9	External Break-In (Asynchronous): A TTL level input with an internal 3.3K pull-up resistor. If this input is pulled low, the Diagnostic Emulator stops executing the target program as through STEP were depressed or an Internal Breakpoint were detected. (If the Diagnostic Emulator is already in PAUSE, this has no effect). This input stops execution even when the breakpoints are not enabled.
Pin 10	External Break-In (Synchronous): Same as pin 9 except this is the clock synchronous input.
Pin 11	Trace Hold (In): A TTL level input with an internal 3.3K pull-up resistor. If the Diagnostic Emulator is executing a target program and this input is pulled low, further updating of the Trace Memory stops, although the program continues to execute. The contents of the Trace Memory are effectively frozen, and can be reviewed later after program execution has been halted.
Pin 12	BKPT A and SA START (Out): A TTL level output providing a high-going pulse at the time breakpoint conditions are satsified for the Breakpoint A Comparator. This signal can be used to trigger an oscilloscope at a particular point of program execution. It can also be used as the START signal for a signature analyzer. This signal may be set high or low under software control when the Diagnostic Emulator is in PAUSE. This permits diagnostic routines to generate sync pulses or signature analyzer START signals under direct program control.
Pin 13	BKPT B and SA STOP (Out): A TTL level output associtated with the Breakpoint B Comparator. It is functionally identical with the BKPT A signal described above.
Pin 20	DATA TERMINAL READY: This signal is driven to a nominal + 12 volts to indicate that the EM-180 is ready to send data. Its signal state does not change.
Pin 22	RUN (Out): A TTL level output that is active (low) if the EM-180 is executing the target program or accessing the target address space.
Pin 23	+ 5 VOLTS (Out): Loading should not exceed .5 amp.
Pin 24	GROUND: This is the return line for the +5 volts avilable on pin 23. This line is internally connected to the signal ground (pin 7).
Pin 25	SIGNATURE CLOCK (Out): A TTL level output signal (¬MREQ) from the CPU. It is primarily used as a clock for signature analysis testing of equipment for which the EM-180 provides the stimulus.

9-2 OPTION SWITCHES

OPEN
OFF
1
ON
0
1 2 3 4 5 6 7 8
CLOSED

SWITCH:

Table 9-2.1. Set-up Characteristics for Serial Port

			DATA BITS PER	STOP
SW6	SW7	SW8	CHARACTER	BITS
0	0	0*	5**	1
0	0	1	5**	1 1/2
1	0	0	6**	1
1	0	1	6**	2
0	1	0	7	1
0	1	1	7	2
1	1	0	8	1	Normal Set-up
1	1	1	8	2

* CLOSED 0, OPEN 1

** Standard EM-180 communications software requires at least 7 bits for operation.

9-3 SERIAL INTERFACE

The format of a serial word is shown in Figure 9-3.1. When no data is being transmitted, the Serial Data Out pin will be at the -12 volt level (marking). When the EM-180 sends a character, there will always be a START bit, followed by 5, 6, 7 or 8 DATA bits, and 1, 1.5 or 2 STOP bits. The number of DATA bits and STOP bits are selected by the Option Switches on the back panel. See Section 9-2 (Option Switches).

The standard EM-180 software transmits and receives ASCII characters which require 7 bits for their representation. For this reason, the option switches must be set for 7 or 8 bit characters for proper operation. Some data terminals require two stop bits for proper operation and the EM-180 will operate with these terminals; one stop bit is recommended for most other terminals because a somewhat higher data rate is obtained if time is not given to unneded stop bits.

The EM-180 with standard software does not send or check parity. However, it is possible to have one of the data bits function as a pariity bit if the parity generation and checking is done by software.

Two additional signals that are used by the EM-180 are the Request-to-Send (Pin 4) output and the Clear-to-Send (Pin 5) input. The EM-180 standard software uses these signals to coordinate the data transfer. When the EM-180 is ready to begin receiving data, it changes the Request-to-Send line from low to high and awaits data transmission. When the EM-180 has finished receiving data, it will return the Request-to-Send line to the low state. When the EM-180 is ready to send a character, the software tests the condition of the Clear-to-Send line and transmission of the character proceeds only if Clear-to-Send is in the high state; the character is held if the signal is in the low state. Thus, a receiving device may control the transfer of data by taking the Clear-to-Send line high when more data is desired and low when not ready for data. The EM-180 may be made to consider the Clear-to-Send line as always high by closing Option Switch 3 on the back panel.

The serial port transmission rate is controlled by the rotary hexadecimal switch in the lower left corner of the back panel. The EM-180 is capable of communicating at baud rates from 50 baud to 19,200 Baud. See Figure 9-3.1.

Figure 9-3.1. Serial Word Format.

- 12V START D0 D1 D2 D3 D4 D5 D6 D7 STOP START D0
- 12V t
t = time of one data element or "baud"

Switch Position	Baud Rate	t
D	50	20	mSEC
C	75	13.33
0	110	9.09
B	134.5	7.43
1	150	6.67
A	200	5
2	300	3.33
9	600	1.67
4	1,200	833	uSEC
5	1,800	556
3, 8	2,400	417
6	4,800	208
7	9,600	104
E, F	19,200	52

9-4 UPLOAD/DOWNLOAD PROTOCOL

DATA RECORD

START CHARACTER BYTE COUNT ADDRESS RECORD TYPE DATA CHECK BYTE

START CHARACTER
An ASCII colon is used to signal the start of a record.

BYTE COUNT
Two ASCII characters representing hexadecimal digits giving the number of data bytes in the record.

ADDRESS
Four ASCII characters representing hexadecimal digits giving the address in target memory where the first of the data bytes of this record is to be located. The following bytes in the record are located in sequentially higher addresses in memory.

RECORD TYPE
Two ASCII characters representing hexadecimal digits that are encoded to designate the record type For data records as defined here the Record Type will always be 00₁₆.

DATA
Each two ASCII characters representing hexadecimal digits give the bit pattern of one eight-bit byte of data. The total number of data bytes in the record is given by the byte count.

CHECK BYTE
Two ASCII characters representing hexadecimal digits giving the value of a check byte. The value of the check byte is the two's complement of the sum of all the other bytes of the record; that is, the byte count plus the first byte of the address plus the second byte of the address plus the record type byte plus all of the data bytes. If the check byte is added to the sum of all the other bytes, the result will be zero. (The addition is performed modulo 256 in that any carry out of an eight bit result is ignored.)

END-OF-FILE RECORD

START CHARACTER BYTE COUNT ADDRESS RECORD TYPE

START CHARACTER
An ASCII colon is used to signal the start of a record.

BYTE COUNT
To ASCII zeros.

ADDRESS FIELD
Four ASCII characters representing hexadecimal zeros, or the starting address of the program.

RECORD TYPE FIELD
Two ASCII characters representing the hexadecimal digits 01.

9-5 EXTERNAL BREAKPOINT

The EM-180 samples the External Breakpoint input at the low-to-high transition of the clock that begins the final T-state of an instruction. If the signal is low at the sample time, the signal is entered into the Trace Memory, thus marking the cycle during which the signal was detected; circuitry in the EM-180 is also armed to halt program execution after completion of the current instruction. When the target program has been halted, the EM-180 firmware will determine which cycle of the last instruction caused the breakpoint and the Trace Memory will be positioned to display that cycle. Figure 9-5.1 shows the timing relationships of the External Breakpoint signal.

Figure 9-5.1. Timing Relationships

Last T State
CLK
External Breakpoint
Set-up: 150 nSEC MIN
Hold: 0 nSEC MIN

SET-UP PRIOR TO LOW-HIGH TRANSITION OF CLK: 150 nSEC MINIMUM.

HOLD TIME AFTER LOW-HIGH TRANSITION OF CLK: 0 nSEC MINIMUM.

9-6 TRACE HOLD

The circuitry controlling the Trace Hold input must ensure that the set-up and hold time requirements are met for reliable operation. The requirements are shown in Figure 9-6.1.

The Trace Hold feature may be used to capture trace data on a selective basis as detailed in the following paragraphs.

Figure 9-6.1. Trace Hold and Timing

¬MREQ/IORQ
¬TRACE HOLD
SET-UP: 30 nS Min.
HOLD: 20 nS Min.

AT LEAST 30 nSEC BEFORE THE LOW TO HIGH TRANSITION OF ¬MREQ OR ¬IORQ.
AT LEAST 20 nSEC AFTER LOW TO HIGH TRANSITION OF ¬MREQ OR ¬IORQ.

9-6.1 WINDOW MODE

Figure 9-6.2. Window Mode Circuit

OFF
Trace Hold
ON
74LS27
BKPT A
BKPT B
¬RUN
+ 5 VOLTS

Trace from Address A to Address B

9-6.2 SELECTIVE TRACE

9-7 SIGNATURE ANALYSIS

The EM-180 Diagnostic Emulator does not contain circuitry for examining signatures at circuit notes. It does, however, contain pre-programmed stimulus routines that may be used to generate the repetitive signals that must be present for the signature analysis concept to work.

Figure 9-7.1 is a simplified microprocessor system diagram and shows a Z-80 processor two ROMs, one RAM, some I/O circuitry and device enable logic. To test a system such as this one, first perform the obvious checks such as measurment of the supply voltages and then connect the EM-180 to the circuit. The system clock may be checked by using the CODE D2 function; the clock frequency displayed by the EM-180 should be one-half of the crystal frequency. Now proceed with signature analysis testing by connecting a signature analyzer (such as the HP 5004A) to the EM-180 Auxiliary Connector (J3, on the back panel of the EM-180) as follows:

SA GROUND	to JE - 24 (GROUND)
SA START	to J3 - 12 (BKPT A and SA START)
SA STOP	to J3 - 13 (BKPT B and SA STOP)
SA CLOCK	to J3 - 25 (SIGNATURE CLOCK)

The selector switches for the START, STOP and CLOCK signals on the signature analyzer should be set for low-to-high edge recognition (buttons out on the HP 5004A).

Figure 9-7.1 Simplified Microprocessor Diagram

(picture)

BINARY ADDRESS TEST (FREE-RUN)

To start with, set both the A and B breakpoint comparators so that they will respond to READ cycles at address 0000₁₆ (See Section 4-1.4). Next, start the binary address routine by depressing the keys for CODE B5. The EM-180 will begin to output incrementing addresses; an SA START pulse and an SA STOP pulse will occur each time address 0000₁₆ is output. The stimulus and signature analyzer are now ready for use.

At this point, the address bus signals may be probed with the signature analyzer and each should display its characteristic signature. The various device enable signals may be probed and, if the system circuitry is working correctly, characteristic signatures will be obtained. Various nodes internal to the Device Enable Logic may also be probed; in short, any circuit point may be tested where the signal present is determined by the address inputs and the RD signal.

In most cases, the data bus cannot be tested with this setup because the data bus signals are not determined by addresses for all possible address values. For example, some addresses may result in floating the data bus; other addresses may select RAMs whose contents are not known. Therefore, to test the data bus using the signature analysis technique, it is necessary to restrict the start-stop window of the signature analyzer so that the data bus is sampled only when addresses are present that should should result in known data on the bus.

Suppose that it is known that ROM 1, in Figure 9-7.1, is enabled by the Device Enable Logic for any address in the range from 1000₁₆ to 17FF₁₆. If the SA START signal could be generated when the incrementing address reaches 1000₁₆ and the SA STOP signal generated when the incrementing address reaches 17FF₁₆, then signatures would be computed only during the time the data bus contained deterministic data. The SA START and SA STOP signals may be easily adjusted to occur at any desired address by setting the appropriate breakpoint values into the A and B breakpoint comparators. For the example just given, set the A comparator to respond to READ cycles at address 1000₁₆ and set the B comparator to respond to READ cycles at address 17FF₁₆. Then test the eight data lines to obtain the characteristic signatures. Note that the signatures obtained depend not only on the details of the circuitry of the system under test, but also on the contents of the ROM involved; consequently, this test also verifies that the ROM contains the same pattern as the ROM for which the reference signatures were originally obtained.

The EM-180 also has a built-in test function for obtaining a signature of a ROM in a system, and no signature analyzer is needed. The test is set up by entering the first and last address of the ROM into the BEG and END registers of the EM-180 to define the range over which the routine will operate. Then start the routine with the Keys for CODE D3. The routine will execute and then display a four-digit hexadecimal signature on the EM-180 front panel. The signature obtained does not have any simple relationship to signatures obtained with the HP 5004A; for one thing, the CODE D3 algorithm operates on all eight data bits of the ROM word simultaneously while the eight signatures obtained by the HP 5004A for a ROM are computed from one "bit slice" of the ROM at a time. In addition, the generating polynomial used by the EM-180 routine differs from that used by the HP 5004A. See Section 7-4 for additional information.

Other routines that are programmed in the EM-180 Diagnostic Emulator may be useful as stimulus routines for signature analysis testing. The CODE B4 routine repetitively stores a data pattern and the complement of that pattern to a selected address. An I/O port, such as the one shown in Figure 9-7.1, may be tested by storing the complementing data to the I/O port and observing the signatures obtained at the output side of the I/O port.

In special cases it may be found necessary to write custom CODE function routines to stimulate a system in a way that useful signatures may be obtained. As an example, consider the problem of obtaining a signature at the outputs of an LSI interface chip such as the Zilog PIO. This device requires that various control registers and data direction bits be set up for the intended application before data transfers are performed. A custom CODE Function routine can easily perform the desired set-up and then generate the stimulus for signature analyzer probing.

For additional information on Signature Analysis testing, see the following publications:

1. "Hexadecimal Signatures Identify Troublespots in Microprocessor Systems", Gary Gordon and Hans Nadig. ELECTRONICS, March 3, 1977.

2. Application Note 222, "A Designer's Guide to Signature Analysis", Hewlett Packard Corporation.

9-8 SOFT SHUTDOWN