| 6-1 | Overview |
| 6-2 | Format Definition |
The disassembly firmware is disabled when the EM-180 is first powered up and must be enabled before use. The following procedure will make the EM-180 ready to operate with an ASCII terminal and disassembly firmware:
Pin 1 - Protective Ground
Pin 2 - Serial Data Out
Pin 7 - Signal Ground
Some RS-232 terminals may also require the following connection:
Pin 20 - Data Terminal Ready
Take care that Pins 10, 11, 12, 13, 22, 23, 24, and 25 are not connected to incompatible circuits. See 9-1, Auxiliary Connector.
2. Set the Baud Rate Selector switches of the EM-180 and the terminal to compatible settings.
3. Check the setting of Option Switch 3. If Option Switch 3 is open (up), then the EM-180 will not output serial data unless the Clear-to-Send signal (Pin 5) is high. If the Clear-to-Send signal is not important in your application, set Option Switch 3 to the CLOSED (down) position and the EM-180 will output data on command regardless of the state of Pin 5.
4. Enable the disassembly firmware by executing the Code Function E1, E2, or E3. The EM-180 is now ready to output to the terminal device. See Table 6-1 for format selection information.
The disassembly firmware may be turned off by executing Code Function E0.
Operate the Em-180 in the normal manner. Any time that the Em-180 transfers from RUN to PAUSE, the disassembly firmware will format and dump a part of the contents of the Trace Memory to the terminal; normally 24 lines of output are produced. The last line output represents the last instruction executed and the firmware will then output the register display.
If the EM-180 is operated in single-step mode, the firmware will output the register display after every instruction.
The disassembly software is designed so that 20 lines of output are produced each time the emulator transfers from RUN to PAUSE; this amount of data provides approximately a full screen on most CRT terminals. If output of the entire contents of the Trace Memory is desired, execute Code Function D8. This Code Function will execute even if disassembly is not enabled, but the disassembly firmware option must be installed on the machine. All of the data in the Trace Memory will be formatted and output. Data output may be suspended for a moment by depressing the EXAM Key; when the Key is released, data output will continue.
NOTE: It is possible that the data recorded in Trace Memory does not represent actual machine execution of a program (for example, a block of data left by a memory diagnostic Code Function or a data transfer Code Function). In such a case, the disassembler will not format and output the data.
Table 6-1. Disassembly Format Selection
| CODE | ||
| FUNCTION | REGISTERS DISPLAYED | FORMAT |
| E0 | —— | (Disable Disassembly) |
| E1 | Flags, A, BC, DE, HL, SP | 80-Character Line |
| E2 | Flags, A, BC, DE, HL | 72-Character Line |
| E3 | Flags, A, BC, DE, HL, IX IY, SP, Flags', A', BC', DE', HL' | Two 72-Character Lines |
Address
The address of the first op-code byte of the instruction.
Op-Code
The operation code of the instruction. Double op-code instructions are displayed with the prefix byte extending to the left of the column of op-code bytes. The two-line register display format will show the IX register contents underneath this field.
Operand
The operand bytes of the instruction (if any).
Op-Code Mnemonic
The operation code of the instruction given in mnemonic form. The two-line register display format will show the IY register contents underneath this field.
Operand
The operand field of the instruction is symbolic format, except that addresses and constants are given as hexadecimal numbers.
Data Transfer
Any data transfer operations that occur as a consequence of the instruction are shown here. The most common formats are:
AAAA>DD
or AAAA<DD
The first format means that the processor wrote data 'DD' to address 'AAAA'. The second format means that the processor read data 'DD' from address 'AAAA'. The other formats are associated with I/O instructions and take the form:
--PP>DD
--PP<DD
The first of these formats means that the processor wrote data 'DD' to output port 'PP'. The second format means that the processor read data 'DD' from input port 'PP'. The two-line register display format will show the stack pointer contents underneath this field.
Data Transfer
Some instructions transfer more than one byte of data. The second byte of a data transfer will be shown in this field. If there are more than two bytes transferred, the additional bytes are shown in fields 6 and 7 on the following line. See, for example, the EX (SP), HL instruction which reads two bytes from the top of stack and then writes two other bytes to the top of stack. All of these transfers are easily seen from the display.
Breakpoint
If a breakpoint occurred during the execution of the instruction on this line, it will be identified in this column by an asterisk ( * ).
The CPU flag register (condition code register) is shown in this field. Each of the five characters in this field represent one of the condition code bits as follows:
| First | - 'S' if sign bit is true. |
| Second | - 'Z' if zero bit is true. |
| Third | - 'H' if half carry bit is true. |
| Fourth | - 'P' if parity/overflow bit is true. |
| Fifth | - 'N' if subtract flag bit is true. |
| Sixth | - 'C' if carry bit is true. |
If any of the condition code bits are not true, the letter is replaced by a period. The two-line register display format will show the alternate (prime) flag register underneath this field.
Accumulator
The content of the accumulator after the execution of the instruction. The two-line register display format will show the alternate (prime) accumulator underneath this field.
BC Register Pair
The content of the BC register pair following the execution of the instruction. The two-line register display format will show the alternate (prime) BC register pair underneath this field.
DE Register Pair
The content of the DE register pair following the execution of the instruction. The two-line register display format will show the alternate (prime) DE register pair underneath this field.
BC Register Pair
The content of the HL register pair following the execution of the instruction. The two-line register display format will show the alternate (prime) HL register pair underneath this field.
Stack Pointer
The content of the stack pointer following the execution of the instruction. This field is not displayed in the 72-character line formats.
Figure 6-2.1 Code E1 80-Character Single-Line Disassembly Format
Address Op-Code Operand Op-Code Mnemonic Operand Data Transfer Data Transfer Breakpoint Flag Register Accumulator BC Register Pair DE Register Pair HL Register Pair Stack Pointer
---- ---- ---- ---- -------- ------- ------ - ----- -- ---- ---- ---- ----
0000 C3 2B00 JP 002B
002B 31 E030 LD SP,30E0
002E 18 03 JR 0033
0033 2A B130 LD HL,(30B1) 30B1<23 30B2<9D
0036 18 0C JR 0044
0044 11 DD62 LD DE,62DD
0047 19 ADD HL,DE
0048 7C LD A,H
0049 B5 OR L
004A 20 08 JR NZ,0054
004C 3A 8034 LD A,(3480) 3480<FF
004F E6 40 AND 40
0051 C2 0D01 JP NZ,010D
010D DF RST 18 30DF>01 30DE>0E
0018 C3 100E JP 0E10
0E10 E3 EX (SP),HL 30DE<67 30DF<01
30DF>00 30DE>00
0E11 D5 PUSH DE 30DD>62 30DC>DD
0E12 F5 PUSH AF 30DB>40 30DA>10
0E13 33 INC SP
0E15 3E CB LD A,CB
0E17 32 7430 LD (3074),A 3074>CB
0E1A 1A LD A,(DE) 0167<3E
0E1B 32 7530 LD (3075),A 3075>3E
0E1E 3E C9 LD A,C9
0E20 32 7630 LD (3076),A 3076>C9
0E23 13 INC DE
0E24 21 9F30 LD HL,309F
0E27 CD 7430 CALL 3074 30DA>0E 30D9>2A
3074>CBFE SET 7,(HL) 309F<C0 309F>C0
3076 C9 RET 30D9<05 30DA<70
7005 FF RST 38 7006<FF 30DA>70*..H... C9 003D 0168 309F 30DB
Figure 6-2.2 Code E2 72 Character Single-Line Disassembly Format
Address Op-Code Operand Op-Code Mnemonic Operand Data Transfer Data Transfer Breakpoint Flag Register Accumulator BC Register Pair DE Register Pair HL Register Pair
---- ---- ---- ---- -------- ------- ------ - ----- -- ---- ---- ----
0000 C3 2B00 JP 002B
002B 31 E030 LD SP,30E0
002E 18 03 JR 0033
0033 2A B130 LD HL,(30B1) 30B1<23 30B2<9D
0036 18 0C JR 0044
0044 11 DD62 LD DE,62DD
0047 19 ADD HL,DE
0048 7C LD A,H
0049 B5 OR L
004A 20 08 JR NZ,0054
004C 3A 8034 LD A,(3480) 3480<FF
004F E6 40 AND 40
0051 C2 0D01 JP NZ,010D
010D DF RST 18 30DF>01 30DE>0E
0018 C3 100E JP 0E10
0E10 E3 EX (SP),HL 30DE<67 30DF<01
30DF>00 30DE>00
0E11 D5 PUSH DE 30DD>62 30DC>DD
0E12 F5 PUSH AF 30DB>40 30DA>10
0E13 33 INC SP
0E15 3E CB LD A,CB
0E17 32 7430 LD (3074),A 3074>CB
0E1A 1A LD A,(DE) 0167<3E
0E1B 32 7530 LD (3075),A 3075>3E
0E1E 3E C9 LD A,C9
0E20 32 7630 LD (3076),A 3076>C9
0E23 13 INC DE
0E24 21 9F30 LD HL,309F
0E27 CD 7430 CALL 3074 30DA>0E 30D9>2A
3074 CBFE SET 7,(HL) 309F<C0 309F>C0
3076 C9 RET 30D9<05 30DA<70
7005 FF RST 38 7006<FF 30DA>70*..H... C9 003D 0168 309F
Figure 6-2.3 Code E3 72-Character Two-Line Disassembly Format
Address Op-Code (IX Register) Operand Op-Code Mnemonic (IY Register) Operand Data Transfer (Stack Pointer) Data Transfer Breakpoint Flag Register (Flag Register') Accumulator (Accumulator') BC Register Pair (BC' Register Pair) DE Register Pair (DE' Register Pair) HL Register Pair (HL' Register Pair)
---- ---- ---- ---- -------- ------- ------ - ----- -- ---- ---- ----
07E4 6F LD L,A
07E5 7C LD A,H
07E6 CE 00 ADC A,00
07E8 27 DAA
07E9 67 LD H,A
07EA 3A 7534 LD (A,3475) 3475<4E
07ED E6 08 AND 08
07EF C9 RET 305A<BB 305B<07
07BB C2 B807 JP NZ,07B8
07B8 CD D007 CALL 07D0 305B>07 305A>BB
07D0 3D DEC A
07D1 78 LD A,B
07D2 A7 AND A
07D3 CA F007 JP Z,07F0
07D6 3A 7E30 LD A,(307E) 307E<57
07D9 83 ADD A,E
07DA 5F LD E,A
07DB 3A 7F30 LD A,(307F) 307F>4E
07DE 8A ADC A,D
07DF 57 LD D,A
07E0 7D LD A,L
07E1 CE 00 ADC A,00
07E3 27 DAA
07E4 6F LD L,A ...... 16 1B00 7D11 2416
IX:3000 IY:0000 SP:305A ...... 00 0000 0000 0000
NOTE:
The assembler uses EM-180 scratch RAM addresses 3100H—32BFH
The line assembler assumes that a terminal is attached to the EM as described in Section 6.1.
NOTE:
Your typed entry will be overtyped by the asembled response unless you map RETURN into RETURN/LINEFEED. This is especially important to note when using a hardcopy terminal.
In the examples shown here, all entries and assembled responses are shown as if there is a RETURN/LINEFEED. (Responses are shown in bold type.)
To invoke the line assembler, enter on the emulator keyboard:
<code> <C> <0>
The following response will appear on the terminal screen:
APPLIED MICROSYSTEMS CORPORATION
Z80 SINGLE LINE ASSEMBLER
VERSION X.X
(C) COPYRIGHT 1983
0000>
At this point, lines may now be entered and assembled into target memory. When you want to stop using the line assembler, type the pseudo-operation "END" after the address prompt as in this example:
F004> LD A,D
F004 7A
F006> END
*** End of Line Assembly ***
The line assembler may be used to invoke the memory disassembler by entering a RETURN as the only entry on a line. This causes the memory disassembler to display the instruction located at the current value of the location counter and increment the location counter.
Example:
F000> <return>
F000 20F2 JR NZ, EFF4
F002> <return>
F002 F620 OR 20
F00C> END <return>
*** End of Line Assembly ***
Table 6.3-1 Assembler Directives
Assembler Directives
| ORG | Sets the address pointer |
| = | Sets the value of a LBL |
| END | Terminates the line assembler |
| DEFT | Defines as ASCII string |
| DEFB | Defines a byte of memory |
| DEFW | Defines a word of memory |
| LBL | A temporary line assembler value |
| $ | Represents the value of the address pointer |
| PRE | Turns preview on or off |
| ORG | Initially the address pointer is 0000H. Use ORG to change the address pointer.
-To change the address pointer to 0064H, enter ORG 100
|
| = | Use the equal sign with LBL to set or recall a local label value.
-To set label 1 to 100H, enter LBL1 = 100H <return> -To see the value of label 3, enter LBL3 = <return>
|
| END | Terminates the line assembler and returns control to the emulator keyboard.
|
| DEFT | To enter a target string into memory, type:
DEFT text text text <return>
|
| DEFB | To enter a single byte directly into memory, type:
DEFB AFH <return>
|
| DEFW | To enter a two-byte word, type:
DEFW AFAFH <return> |
| $ | The current value of the address pointer. |
| PRE | Toggles between the two forms of the line assembler prompt: |
| -The simple address pointer > | |
| -A preview of the code at the address pointer. | |
| LBL | The Single Line Assembler provides up to ten local labels in the form of LBL0 through LBL9. |
NOTE:
No labels are initialized upon entering the Line Assembler. You must define a label before using it. The allowable label operations are defined below.
| LBLn = | Prints the current label value |
| LBLn = number | Assigns the value "number" to the label |
| LBLn = $ | Assigns the value of the current location counter to the label |
Any mnemonic and all assembler directives except "ORG" and "END" may be preceded by a label.
| Ctrl-H or Backspace | Deletes the character before the cursor |
| Ctrl-I or Tab | Enters spaces to the next tab stop in the line (tab stops are 10,20) |
| Form | Format |
| Decimal | 100 |
| Hexadecimal | 100H |
| Binary | 10110B |
| Octal | 7342O or 7342Q |
<reg> <4> <load data> ... enter starting address
<reg> <5> <load data> ... enter ending address
Next, start the disassembly by entering on the emulator keyboard:
<code> <C> <A>
You can control the display by entering
Ctrl-S (stop)
or
Ctrl-Q (resume)
| F000 | C206F0 | JP NZ, F006 |
| F003 | E3 | EX (SP), HL |
| F004 | C5 | PUSH BC |
| F005 | C9 | RET |
| Syntax error | Indicates a syntax error in the input line |
| Target write error | Indicates failure of opcode store operation to target system (or overlay) |
If you have a syntax error, retype your input line. If you have a target write error, there are several possible conditions:
• The RAM overlay switches are not on.
• You may be trying to store code in an incorrect area, such as an address range where no memory is available.
• There is a possible problem in the target system, such as defective RAM or an addressing error (trying to write ROM).