SECTION 4

EM-180 FUNCTIONS

EM-180 FUNCTIONS
A basic function of the EM-180 is to emulate the target system microprocessor. Effectively, the Diagnostic Emulator is a pin-compatible functional replacement for the microprocessor in the target system. The unit is designed to meet the timing specifications of the emulated processor and to minimize the increase in electrical loading of the user's system.

The EM-180 is always in one of two modes: RUN or PAUSE. If in the RUN mode, the EM-180 is emulating the target system microprocessor and executing the target system program at full system speed. The Trace Memory will be active (unless inhibited by external control) and all bus cycles of the emulated microprocessor are recorded for possible later display. In the PAUSE mode, emulation of the target system microprocessor is suspended and the operator is able to perform other functions such as manually examining or altering memory locations, I/O ports or internal registers of the emulated microprocessor; the operator may also review the history of the target program execution from the Trace Memory or execute one of the Code Function routines.

4-1 EXECUTION CONTROL

4-1.0 RESET Keyswitch

4-1.1 RUN Keyswitch

4-1.2 RUN BKPT Keyswitch

4-1.3 STEP Keyswitch

1. The processor stops executing the target program.

2. The processor registers are saved in internal scratch pad memory and are accessible for display or alteration.

The operator, in effect, freezes the target program execution at the point reached when STEP was depressed. The operator then has several options:

1. Continue executing the program at full speed by pressing RUN.

2. Continue executing the program one instruction at a time by pressing STEP for each additional instruction execution.

3. Examine or change the contents of any of the processor registers.

4. Examine any memory or I/O address, and if the location is writable, store new data in it.

5. Review the last 252 bus cycles performed by the processor by decrementing through the Trace Memory.

The state of the target program is not changed by any of these operations (except as purposely altered by the operator) and program execution may be continued from the point where it stopped.

The program may be executed one instruction at a time by pressing STEP once for each instruction. If STEP is pressed and held down, the Diagnostic Emulator begins stepping at about seven instructions per second. The step rate than accellerates gradually from 7 steps per second toa bout 75 steps per second. Execution stops again if the keyswitch is released.

Table 4-1.1 Display Panel Indicators

FAULT GROUP

	ILLUMINATES IF:
CLK	Target system clock not operating.
	Target system clock is low in frequency.
	EM-180 not connected to target system.
RESET	Processor and Diagnostic Emulator held in Reset by a low on the RESET terminal of the microprocessor socket.

MACHINE CYCLE GROUP

	ILLUMINATES IF:
M1	Displayed machine cycle is the first op-code fetch cycle of an instruction.
M1'	Displayed machine cycle is the second op-code fetch of an instruction.
BKPT	Breakpoint. Conditions set up for an output fromt he breakpoint circuitry were satisfied during the displayed machine cycle.
EXT	External. External Breakpoint inupt low (active) during displayed machine cycle.
IORQ	Input/Output Request. Machine cycle being displayed is a data transfer from an input port address or to an output port address.
IACK	Interrupt Acknowledge. Machine cycle being displayed is an interrupt acknowledge cycle.
RD	Read. Machine cycle being displayed is a read from memory or read from I/O cycle.
WR	Write. Machine cycle being displayed is a write to memory or write to I/O cycle.

FLAGS

	ILLUMINATES IF:
S	Sign bit is true.
Z	Zero bit is true.
H	Half-Carry bit is true.
P/V	Parity/Overflow bit is true.
N	Add/Subtract flags is true.
C	Carry bit is true.

CPU STATUS

	ILLUMINATES IF:
IENA	Enabled processor is ready to respond to an interrupt. (Interrupts enabled)
INT	Interrupt. The interrupt input (pin 16) of the Z-80 is low (active).
NMI	Non-Maskable Interrupt. The NMI input (pin 17) of the Z-80 is active.
BUSR	Bus Request. The BUSRQ input of the Z-80 is low (active).
Wait	Wait input (pin 24) of Z-80 is low. CPU is waiting. If the CPU is working with a system that requires some wait states, the indicator may be more or less dimly lit.
Halt	Processor has executed a HALT instruction and has entered the HALT state.
Pause	Real-time emulation of the target program is suspended and the Diagnostic Emulator is awaiting another command.
BKPT ENA	Breakpoint Enable. Illuminate if the RUN BKPT detect circuitry is armed.

4-1.4 Breakpoint System

It is also possible to configure the breakpoint system so that a specified relationship must hold between the A and B breakpoint comparators before PAUSE occurs. The relationships that may be specified are the following:

1.	A or B	Break if condition A or condition B (or both) is found.
2.	A then B.	Break if condition A is found followed some time later by condition B.
3.	A<—>B	Break if any address in the range from A to B (inclusive) is found.
4.	<—A—B—>	Break if any address outside of the range from A to B is found. (including addresses A and B.)

Table 4-1.2. Breakpoint Qualifiers

0 - Disable	4 - Not Used	C - A or B
1 - Memory Read	5 - I/O Read	D - A then B
2 - Memory Write	6 - I/O Write	E - Range A to B
3 - Memory Read/Write	7 - I/O Read/Write	F - Range outside A to B

The various breakpoint possiblities are set up by simple keystroke sequences. The breakpoint address and the breakpoint qualifiers may be changed independently of each other at any time the emulator is in the pause mode.

Some examples of these sequences follow.

EXAMPLE:
Set up breakpoint comparator A to respond to read or write cycles at address 4300₁₆; disable comparator B.

KEYSTROKE SEQUENCE:

[BKPT A] [4] [3] [0] [0] Set breakpoint address.

[BKPT A] [3] Set qualifier 3 (memory R/W).

Press and hold down BKPT A Key while qualifier is entered.

[BKPT B] [0] Set qualifier 0 (Disable).

Press and hold down BKPT B Key while qualifier key is entered.

On power up, the EM-180 sets the qualifiers for both breakpoint comparators for the A OR B relation (comparators operating independently of each other) and the memory read/write qualifier. The address to which each comparator is initialized is 0000₁₆. In the preceding example it was not necessary to alter the relationship holding between the two comparators, so the default A OR B relationship was not altered.

EXAMPLE:
Set up breakpoint comparator A to repond to read cycles only at memory address 8A72₁₆, and breakpoint comparator B to respond to write cycles to I/O port 13₁₆.

KEYSTROKE SEQUENCE:

[BKPT A] [8] [A] [7] [2] Set A breakpoint address.

[BKPT A] [1] Set A qualifier to 1 (MEMORY read).

Press and hold down BKPT A Key while qualifier is entered.

[BKPT B] [X] [X] [1] [3] Set B breakpoint address.

[BKPT B] [6] Set B qualifier to 6 (I/O WRITE).

Press and hold down BKPT B Key while qualifier is entered.

EXAMPLE:
Set up write-only breakpoint range from 4307₁₆ to FFFF₁₆.

KEYSTROKE SEQUENCE:

[BKPT A] [4] [3] [0] [7] Set A to range beginning (4307₁₆).

[BKPT A] [E] [3] Set qualifier to 3 (Memory R/W) and E (Range A to B).

Press and hold down BKPT A Key while qualifiers are entered.

[BKPT B] [F] [F] [F] [F] Set B to range end (FFFF₁₆).

In this example, two qualifiers were entered: one to specify that write cycle detection was desired and a second to specify that the A and B comparators are to work together to define a continuous range. With the specifications made as shown, the breakpoint circuitry whill repond to any write cycle to any address in the range of 4307₁₆ to FFFF₁₆. Note that it was not necessary to specify any qualifiers for the B comparator; this is because the two comparators are linked together to provide address range detection and the qualifiers entered for A apply also to B.

EXAMPLE:
Set up sequential breakpoint detection such that target program execution will halt after the A comparator has detected memory address EB22₁₆ and then the B comparator has detected a write to I/O port 48₁₆.

KEYSTROKE SEQUENCE:

[BKPT A] [E] [B] [2] [2] Set A to memory address EB22₁₆.

[BKPT A] [D] [1] Set A qualifiers to 1 (Memory Read) and D (A then B).

Press and hold down BKPT A Key while qualifiers are entered.

[BKPT B] [4] [8] Set B to port address 48₁₆.

[BKPT B] [6] Set B qualifier to 6 (I/O Write).

Press and holdd down BKPT B Key while qualifiers are entered.

In this example, separate qualifiers were required for the A and B comparators because no restriction on the type of cycle is implied by the A then B relation as is the case with the RANGE qualifiers.

Table 4.1.3 shows the permissible breakpoint combinations.

Table 4.1.3. Breakpoint Combinations

	C	D	E	F
	A or B	A then B	A<—>B	<—A—B—>
0 DISABLE	v	v	v	v
1 MEM RD	v	v	*	*
2 MEM WR	v	v	*	*
3 MEM R/W	v	v	*	*
4	Not Used	Not Used	Not Used	Not used
5 I/O RD	v	v	*	*
6 I/O WR	v	v	*	*
7 I/O R/W	v	v	*	*

* Breakpoints A and B will both be of same type, such as MEM RD or I/O R/W. Type may be specified for either A or B and will be in effect for both comparators.

4-1.5 TRACE MEMORY

To review the Trace Memory contents, the EM-180 must be paused. The PAUSE mode is entered automatically when the program encounters a breakpoint, or it can be entered manually by depressing STEP. When the program enters PAUSE as a consequence of depressing the STEP Key, the Display shows the fetch cycle address and data for the last instruction recorded.

When a breakpoint event triggers PAUSE*, the Display shows the cycle where the breakpoint was detected, and the user can easily review the program activites leading up to the event. Depressing DEC allows the user to examine the last 252 bus cycles of program activity prior to the breakpoint. Depressing INC allows the user to review forward up to the last cycle traced. Depressing STEP advances the target program past the breakpoint event, one instruction at a time. Depressing TRACE allows the user to return to Trace Memory again after selecting another mode (i.e., MEM ADDR, I/O ADDR, etc.) and return the original program event or bus cycle to the display. The TRACE Key has no effect unless the program is already in PAUSE. STEP actually causes the emulator to execute another program instruction and this instruction is entered into the Trace Memory like all others.

The Z-80 machine instructions may have one or several bus cycles per instruction. The following two examples illustrate displayed Trace Memory contents, first after executing a simple instruction and then after a more complex one.

EXAMPLE 1   LD B, C

Cycle	Addr	Data	Fetch	RD	WR
1	4000	41	X	X

Single bus cycle instruction: Move contents of C register to B register. Assume the instruction location is address 4000₁₆ in the target memory. The Trace Memory records a bus cycle with the address of 4000₁₆, data of 41₁₆ and control bits indicating that it is a fetch operation and a read cycle.

EXAPLE 2   LD (07055H), HL

Cycle	Addr	Data	Fetch	RD	WR
1	4000	22	X	X
2	4001	55		X
3	4002	70		X
4	7055	34			X
5	7056	12			X

Five bus cycle instruction: Cycle one fetches op-code 22 of the LD instruction located at address 4000₁₆. Cycles two and three read low order and high order bytes (55₁₆ and 70₁₆) of the 16-bit address located at 4001₁₆ and 4002₁₆. Cycles four and five write the contents of the HL register pair (34₁₆ and 12₁₆). The Trace Memory records all five bus cycles of the instruction. The address location, program data and op-code cycle are shown on the Display Panel for each bus cycle of the instruction. If the EM-180 had entered PAUSE and displayed Cycle 1 (the OP-CODE fetch), then the INC Key would be used to advance through the Trace Memory and observe the subsequent bus cycles.

Normally, the INC and DEC Keys move the trace index one cycle at a time. If the operator depresses and holds down the TRACE Key, however, the INC and DEC keys will cause the next or previous fetch cycle to be displayed without stopping on other machine cycles.

4-2 EXAMINATION AND ALTERATION OF CPU REGISTERS

Register data is accessed for display by using the blue REG Keyswitch, followed by one of the hexadecimal keyswitches. This designates which register should be displayed. Table 4-2.1 shows the registers selected by the various keyswitches. Note that 4 through 7 do not correspond to actual Z-80 registers. These keyswitches are used to set up parameters for the Built-In test routines or User Code Functions. These Code Functions are described in alter sections. (See Section 7 and Section 8).

Examples of readout and alteration of CPU registers:

EXAMPLE:

[REG] [B] B register contents displayed on address

[REG] [B] [LOAD DATA] [3] [F] B register is accessed and then overwritten with data 3F₁₆.

[REG] [1 SP] Stack Pointer is accessed and displayed on 16-bit address display.

[REG] [2 HL] [LOAD DATA] [3] [C] [0] [0] HL Register Pair is accessed, and then the contents are overwritten with 3C00₁₆.

The prime registers are accessed by depressing the hexadecimal key a second time. For example, the B-prime register is accessed in the following example:

EXAMPLE:

[REG] [B] [B]

The first key depression will access and display the B register, but depressing the key a second time switches the display to the prime register. If the B key is depressed yet again, the display goes back to the regular register again.

All register contents are displayed on the Address Display. If the register has 16 bits, then all four digits of the display will be illuminated. If the register has eight bits, then the value is shown on the two low-order digits of the Address Display.

The Data Display is used for feedback to the operator of the register that has been selected. If the stack pointer is selected, the Data Display will show a '1' since the 1 digit key is used to select that register. If the B register is selected as in the example preceding, the Data Display will show a 'B'; if the B-prime register is selected, then a '1B' will be displayed.

Table 4-2.1. Keyboard Designators (After REG Keyswitch is Pressed)

	(first key push)	(second key push)
KEY	REGISTER	REGISTER	DESCRIPTION
0	PC		Program Counter
1	SP		Stack Pointer
2	HL	HL'	HL Register Pair and Prime
3	DE	DE'	DE Register Pair and Prime
4	BEG*		Begin Address (for programmed tests)
5	END*		End Address (for programmed test)
6	ADDR*		Address (programmed test parameter)
7	DATA*		Data (programmed test parameter)
8	IX		IX Register
9	IY		IY Register
A	A	A'	Accumulator and Prime
B	B	B'	B Register and Prime
C	C	C'	C Register and Prime
D	D	D'	D Register and Prime
E	E	E'	E Register and Prime
F	FLAGS	FLAGS'	Flags and Prime

* Not an actual Z-80 register

4-3 EXAMINATION AND ALTERATION OF MEMORY LOCATIONS

EXAMPLE:

[MEM ADDR] [4] [3] [1] [A] [EXAM] Address 431A₁₆ is entered, and when EXAM is pressed, the EM-180 will read from address 431A₁₆ and display the data obtained.

If the operator wishes to review a group of sequential memory location, this may be done by entering the initial address and examining that location as above; then examine successive locations by depressing INC.

EXAMPLE:

[MEM ADDR] [4] [3] [0] [0] [EXAM] Examine data at 4300₁₆.

[INC] Examine data at 4301₁₆

.
.
. etc. Examine data at successive location, etc.

A memory location may be altered by entering an address, as shown above,

then entering data using LOAD DATA and finally storing the data to the selected memory address using STORE.

EXAMPLE:

[MEM ADDR] [1] [3] [F] [E] [LOAD DATA] [5] [5] [STORE]

The above sequence writes the data 55₁₆ to memory address 13FE₁₆ in the target system.

Sequential locations may be quickly altered by incrementing the address after each data entry operation. For example, the following keystroke sequence enters a short program fragment into memory:

EXAMPLE:

[MEM ADDR] [0] [8] [0] [0] Enter initial address 0800₁₆.

[LOAD DATA] [C] [3] [INC] Enter data C3₁₆ then store the data to 0800₁₆ and increment to 0801₁₆.

[0] [0] [INC] Enter data 00₁₆ then store the data to 0801₁₆ and increment to 0802₁₆.

[0] [8] [INC] Enter data 08₁₆ and store to 0802₁₆; increment to 0803₁₆, etc.

The EM-180 does not require redundant keystrokes. The unit assumes that if the operator has entered new data while a particular memory address is accessed, then the operator wants to store that data before going to the next address.

In all of the above examples in which INC was used, DEC (decrement) could also have been used.

4-4 EXAMINATION AND ALTERATION OF I/O PORTS

EXAMPLE:

[I/O ADDR] [0] [3] [EXAM] Read and display data at Input Port 3.

[I/O ADDR] [1] [B] [LOAD DATA] [A] [0] [STORE] Data A0₁₆ is written to Output Port 1B₁₆. (No READ cycle was performed at Port 1B.)