7800 mini-ultra cartridge board

Description:

The 7800 mini-ultra board is a cartridge board for Atari 7800 games which use either no bank switching or the standard Atari bank switching and do not need RAM or a POKEY. Easy-to-configure jumpers support 8K to 256K, bankswitched or not. The board can also be made to support 512K or 1 megabyte with a different GAL chip and extra pull-up resistors.

The board fits in a standard open-ended (doorless) 2600/7800 cartridge case, and can be assembled using basic soldering skills and readily available parts.

Parts:

Part	Part type	Description
U1	EPROM	any size EPROM from 2764 to 27020
U2	74LS02 or GAL20V8	address decoder / bank switch
C1	0.1µF (104)	bypass capacitor (only one used due to the chip layout)
R1-R6	4.7KΩ	pull-up resistors for bank-switching, 1/4 or 1/8 watt
W1-W9	—	configuration jumpers

Configurations:

Size	Banked?	U1	U2	R1	R2	R3	R4	R5	R6	W1	W2	W3	W4	W5	W6	W7	W8	W9
8K	N	2764	74LS02	-	-	-	-	-	-	X	X	U	U	U	-	-	-	-
16K	N	27128	74LS02	-	-	-	-	-	-	X	X	U	U	U	-	-	-	-
32K	N	27256	74LS02	-	-	-	-	-	-	X	X	L	U	U	-	-	-	-
48K	N	27512	74LS02	-	-	-	-	-	-	-	-	L	L	U	-	-	-	-
64K	Y	27512	GAL20V8	X	X	-	-	-	-	-	-	L	L	U	-	-	-	-
128K	Y	27010	GAL20V8	X	X	X	-	-	-	-	-	L	L	U	U	U	-	-
256K	Y	27020	GAL20V8	X	X	X	X	-	-	-	-	L	L	L	U	U	-	-
512K	Y	27040	GAL22V10	X	X	X	X	X	-	-	-	L	L	L	U	U	X	-
1M	Y	27080	GAL22V10	X	X	X	X	X	X	-	-	L	L	L	U	U	X	X

X = installed, - = open, U = upper pair (away from chips), L = lower pair (closer to chips)

Notes:

a 74HCT02 can be used instead of a 74LS02.
a PALCE20V8 can be used instead of a GAL20V8.
the GAL20V8 must be programmed before installation.
due to different pinouts and special timing requirements, flash chips can not be used in place of EPROMs

Assembly instructions:

Determine the board configuration using the above table.
Set the configuration jumpers on the front of the board using solder blobs. The best way is to quickly heat and apply solder to each pad, then drag the soldering iron back across the gap while applying more solder. When configuring a stack of boards, this method takes about 10 seconds per board.
Install and solder R1-R4 on the front of the board, as needed for the board configuration.
Install and solder C1 on the front of the board.
Install and solder U2 on the back of the board. Because the pins will get in the way of the EPROM, use diagonal cutters to clip about 1mm from all but the upper-left and lower-right pins (pins facing you) before inserting the chip into the board. The two longer pins should be bent down to secure the chip to the board before soldering.
Install U1 on the front of the board. You should cover the window with a UV-opaque sticker to prevent accidental erasure of the EPROM. Note that if a socket is used, the board will not fit into a standard cartridge case unless a very low profile socket is used.
You can now put the board into a cartridge case.

Programming information for bank switching:

Standard Atari 64K/128K bank switching uses a single ROM, which is mapped into three different areas. The last bank appears at $C000-$FFFF, the next-to-last bank appears at $4000-$7FFF, and the area from $8000-$BFFF is bank-switched.

The bank is selected by writing to any address in the $8000-$BFFF region, with the low bits of the data containing the bank number. 144K cartridges add a separate 16K rom that appears in the $4000-$7FFF region, but this can be simulated by using the next-to-last bank of a 256K configuration.

Jumper information:

W1: connects A14 to pin 8 of the 7402 for a non-bankswitched configuration
W2: connects A15 to pin 9 of the 7402 for a non-bankswitched configuration
W3: connects bank-select A14 (L) or +5V (U) to pin 27 of a 28-pin EPROM / pin 29 of a 32-pin EPROM
W4: connects bank-select A15 (L) or +5V (U) to pin 1 of a 28-pin EPROM / pin 3 of a 32-pin EPROM
W5: connects bank-select A17 (L) or +5V (U) to pin 28 of a 28-pin EPROM / pin 30 of a 32-pin EPROM
W6: connects bank-select A18 (L) or +5V (U) to pin 31 of a 32-pin EPROM
W7: connects bank-select A19 (L) or +5V (U) to pin 1 of a 32-pin EPROM
W8: connects D4 to U2 pin 4 for 512K configuration
W9: connects D5 to U2 pin 23 for 1M configuration

R1: pull-up resistor for bank-select A14
R2: pull-up resistor for bank-select A15
R3: pull-up resistor for bank-select A16
R4: pull-up resistor for bank-select A17
R5: pull-up resistor for bank-select A18
R6: pull-up resistor for bank-select A19

Jumper configuration quick-reference:

GAL programming file:

Note: the test vectors are known to work with the Needham Electronics DOS programming software, specifically with an EMP-20 programmer. They are known to not work with a recent version of BP Microsystems software on a CP-1128 programmer. Caveat usor.

File 78sc_low.jed:

Chip type = 20V8R
Source file: 78sc_low.pal
*
QP24*    N 24 pins * 
QF2706*  N 2706 fuses *
QV0022*  N 22 test vectors *
F0*      N default fuse state *
G0*      N don't blow the security fuse *

L0000
1111111111111111111111111111111111111111
1011011111111011011111111111111111111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L0320
0111111111110111101111111111111111111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L0640
1111111111111111111111111111111111111111
0111111111111111011111111111111111111111
0111111111110111111111111111111111111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L0960
1111111111111111111111111111011111111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L1280
1111111111111111111111111111111101111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L1600
1111111111111111111111111111111111110111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L1920
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L2240
1111111111111111111111111111111111111111
1111111111111011111111111111111111111111
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000*

L2560
01011110*

L2568
0000000000000000000000000000000000000000000000000000000000000000*

L2632
11100011*

L2640
1111111111111111111111111111111111111111111111111111111111111111*

L2704
0*

L2705
1*

C3F6A*

N test vectors *

V0001 N00N00NNNNNNNNLNNNNHNHNN*
V0002 N00N01NNNNNNNNLNNNNHNHNN*
V0003 N00N10NNNNNNNNHNNNNHNHNN*
V0004 N00N11NNNNNNNNHNNNNHNHNN*
V0005 N01N00NNNNNNNNLNNNNHNHNN*
V0006 N01N01NNNNNNNNLNNNNHNLNN*
V0007 N01N10NNNNNNNNHNNNNHNHNN*
V0008 N01N11NNNNNNNNHNNNNHNHNN*
V0009 N10N00NNNNNNNNLNNNNHNHNN*
V0010 N10N01NNNNNNNNLNNNNLNHNN*
V0011 N10N10NNNNNNNNHNNNNLNHNN*
V0012 N10N11NNNNNNNNHNNNNLNHNN*
V0013 N11N00NNNNNNNNLNNNNHNHNN*
V0014 N11N01NNNNNNNNLNNNNLNHNN*
V0015 N11N10NNNNNNNNHNNNNLNHNN*
V0016 N11N11NNNNNNNNHNNNNLNHNN*
V0017 CNNNNNNN010N0NNNLHLNNNNN*
V0018 0NNNNNNN101N0NNNLHLNNNNN*
V0019 CNNNNNNN101N0NNNHLHNNNNN*
V0020 0NNNNNNN010N0NNNHLHNNNNN*
V0021 CNNNNNNN010N1NNNZZZNNNNN*
V0022 0NNNNNNN101N0NNNLHLNNNNN*

0000

File 78sc_meg.jed:

(not tested yet)